? semiconductor components industries, llc, 2005 february, 2005 ? rev. 5 1 publication order number: mc14013b/d mc14013b dual type d flip-flop the mc14013b dual type d flip?flop is constructed with mos p?channel and n?channel enhancement mode devices in a single monolithic structure. each flip?flop has independent data, (d), direct set, (s), direct reset, (r), and clock (c) inputs and complementary outputs (q and q ). these devices may be used as shift register elements or as type t flip?flops for counter and toggle applications. features ? static operation ? diode protection on all inputs ? supply voltage range = 3.0 vdc to 18 vdc ? logic edge?clocked flip?flop design ? logic state is retained indefinitely with clock level either high or low; information is transferred to the output only on the positive?going edge of the clock pulse ? capable of driving two low?power ttl loads or one low?power schottky ttl load over the rated temperature range ? pin?for?pin replacement for cd4013b ? pb?free packages are available* maximum ratings (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage range ?0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) ?0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 1) 500 mw t a ambient temperature range ?55 to +125 c t stg storage temperature range ?65 to +150 c t l lead temperature (8?second soldering) 260 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. temperature derating: plastic ap and d/dwo packages: 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. marking diagrams 1 14 pdip?14 p suffix case 646 mc14013bcp awlyyww soic?14 d suffix case 751a tssop?14 dt suffix case 948g 1 14 14013b awlyww 14 013b alyw 1 14 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week soeiaj?14 f suffix case 965 1 14 mc14013b awlyww see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information http://onsemi.com
mc14013b http://onsemi.com 2 truth table inputs outputs clock 2 data reset set q q 0 0 0 0 1 1 0 0 1 0 x 0 0 q q x x 1 0 0 1 x x 0 1 1 0 x x 1 1 1 1 x = don't care 2 = level change block diagram 10 11 9 8 4 3 5 6 12 13 2 1 s s r r d c d c q q q q v dd = pin 14 v ss = pin 7 11 12 13 14 8 9 10 5 4 3 2 1 7 6 r b c b q b q b v dd s b d b r a c a q a q a v ss s a d a pin assignment ordering information device package shipping 2 mc14013bcp pdip?14 500 units / rail mc14013bcpg pdip?14 (pb?free) 500 units / rail MC14013BD soic?14 55 units / rail MC14013BDg soic?14 (pb?free) 55 units / rail MC14013BDr2 soic?14 2500 units / tape & reel MC14013BDr2g soic?14 (pb?free) 2500 units / tape & reel MC14013BDtr2 tssop?14* 2500 units / tape & reel mc14013bf soeiaj?14 50 units / rail mc14013bfel soeiaj?14 2000 units / tape & reel 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb?free. no change
mc14013b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) ?????????? ?????????? ???? ???? ??? ??? v dd ????? ????? ? 55 c ????????? ????????? 25 c ????? ????? 125 c ??? ??? ?????????? ?????????? characteristic ???? ???? symbol ??? ??? v dd vdc ??? ??? min ??? ??? max ???? ???? min ??? ??? typ (2) ???? ???? max ??? ??? min ??? ??? max ??? ??? unit ?????????? ? ???????? ? ?????????? output voltage a0o level v in = v dd or 0 ???? ? ?? ? ???? v ol ??? ? ? ? ??? 5.0 10 15 ??? ? ? ? ??? ? ? ? ??? ? ? ? ??? 0.05 0.05 0.05 ???? ? ?? ? ???? ? ? ? ??? ? ? ? ??? 0 0 0 ???? ? ?? ? ???? 0.05 0.05 0.05 ??? ? ? ? ??? ? ? ? ??? ? ? ? ??? 0.05 0.05 0.05 ??? ? ? ? ??? vdc ?????????? ? ???????? ? ?????????? v in = 0 or v dd a1o level ???? ? ?? ? ???? v oh ??? ? ? ? ??? 5.0 10 15 ??? ? ? ? ??? 4.95 9.95 14.95 ??? ? ? ? ??? ? ? ? ???? ? ?? ? ???? 4.95 9.95 14.95 ??? ? ? ? ??? 5.0 10 15 ???? ? ?? ? ???? ? ? ? ??? ? ? ? ??? 4.95 9.95 14.95 ??? ? ? ? ??? ? ? ? ??? ? ? ? ??? vdc ?????????? ? ???????? ? ? ???????? ? ?????????? input voltage a0o level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) ???? ? ?? ? ? ?? ? ???? v il ??? ? ? ? ? ? ? ??? 5.0 10 15 ??? ? ? ? ? ? ? ??? ? ? ? ??? ? ? ? ? ? ? ??? 1.5 3.0 4.0 ???? ? ?? ? ? ?? ? ???? ? ? ? ??? ? ? ? ? ? ? ??? 2.25 4.50 6.75 ???? ? ?? ? ? ?? ? ???? 1.5 3.0 4.0 ??? ? ? ? ? ? ? ??? ? ? ? ??? ? ? ? ? ? ? ??? 1.5 3.0 4.0 ??? ? ? ? ? ? ? ??? vdc ?????????? ? ???????? ? ? ???????? ? ?????????? (v o = 0.5 or 4.5 vdc) a1o level (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) ???? ? ?? ? ? ?? ? ???? v ih ??? ? ? ? ? ? ? ??? 5.0 10 15 ??? ? ? ? ? ? ? ??? 3.5 7.0 11 ??? ? ? ? ? ? ? ??? ? ? ? ???? ? ?? ? ? ?? ? ???? 3.5 7.0 11 ??? ? ? ? ? ? ? ??? 2.75 5.50 8.25 ???? ? ?? ? ? ?? ? ???? ? ? ? ??? ? ? ? ? ? ? ??? 3.5 7.0 11 ??? ? ? ? ? ? ? ??? ? ? ? ??? ? ? ? ? ? ? ??? vdc ?????????? ? ???????? ? ? ???????? ? ?????????? output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) ???? ? ?? ? ? ?? ? ???? i oh ??? ? ? ? ? ? ? ??? 5.0 5.0 10 15 ??? ? ? ? ? ? ? ??? 3.0 0.64 1.6 4.2 ??? ? ? ? ? ? ? ??? ? ? ? ? ???? ? ?? ? ? ?? ? ???? 2.4 0.51 ? 1.3 ? 3.4 ??? ? ? ? ? ? ? ??? 4.2 0.88 2.25 ? 8.8 ???? ? ?? ? ? ?? ? ???? ? ? ? ? ??? ? ? ? ? ? ? ??? 1.7 ? 0.36 0.9 ? 2.4 ??? ? ? ? ? ? ? ??? ? ? ? ? ??? ? ? ? ? ? ? ??? madc ?????????? ? ???????? ? ? ???????? ? ?????????? (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) ???? ? ?? ? ? ?? ? ???? i ol ??? ? ? ? ? ? ? ??? 5.0 10 15 ??? ? ? ? ? ? ? ??? 0.64 1.6 4.2 ??? ? ? ? ? ? ? ??? ? ? ? ???? ? ?? ? ? ?? ? ???? 0.51 1.3 3.4 ??? ? ? ? ? ? ? ??? 0.88 2.25 8.8 ???? ? ?? ? ? ?? ? ???? ? ? ? ??? ? ? ? ? ? ? ??? 0.36 0.9 2.4 ??? ? ? ? ? ? ? ??? ? ? ? ??? ? ? ? ? ? ? ??? madc ?????????? ?????????? input current ???? ???? i in ??? ??? 15 ??? ??? - ??? ??? 0.1 ???? ???? e ??? ??? 0.00001 ???? ???? 0.1 ??? ??? - ??? ??? 1.0 ??? ??? adc ?????????? ?????????? input capacitance (v in = 0) ???? ???? c in ??? ??? - ??? ??? - ??? ??? - ???? ???? - ??? ??? 5.0 ???? ???? 7.5 ??? ??? - ??? ??? - ??? ??? pf ?????????? ? ???????? ? ? ???????? ? ?????????? quiescent current (per package) ???? ? ?? ? ? ?? ? ???? i dd ??? ? ? ? ? ? ? ??? 5.0 10 15 ??? ? ? ? ? ? ? ??? ? ? ? ??? ? ? ? ? ? ? ??? 1.0 2.0 4.0 ???? ? ?? ? ? ?? ? ???? ? ? ? ??? ? ? ? ? ? ? ??? 0.002 0.004 0.006 ???? ? ?? ? ? ?? ? ???? 1.0 2.0 4.0 ??? ? ? ? ? ? ? ??? ? ? ? ??? ? ? ? ? ? ? ??? 30 60 120 ??? ? ? ? ? ? ? ??? adc ?????????? ? ???????? ? ? ???????? ? ?????????? total supply current (3) (4) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) ???? ? ?? ? ? ?? ? ???? i t ??? ? ? ? ? ? ? ??? 5.0 10 15 ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? i t = (0.75 a/khz) f + i dd i t = (1.5 a/khz) f + i dd i t = (2.3 a/khz) f + i dd ??? ? ? ? ? ? ? ??? adc 2. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. 3. the formulas given are for the typical characteristics only at 25 c. 4. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l ? 50) vfk where: i t is in a (per package), c l in pf, v = (v dd ? v ss ) in volts, f in khz is input frequency, and k = 0.002.
mc14013b http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? switching characteristics (5) (c l = 50 pf, t a = 25 c) ??????????????? ??????????????? characteristic ????? ????? symbol ???? ???? v dd ???? ???? min ???? ???? typ (6) ???? ???? max ??? ??? unit ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? output rise and fall time t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.55 ns/pf) c l + 9.5 ns ????? ? ??? ? ? ??? ? ????? t tlh , t thl ???? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? ? ? ? ???? ? ?? ? ? ?? ? ???? 100 50 40 ???? ? ?? ? ? ?? ? ???? 200 100 80 ??? ? ? ? ? ? ? ??? ns ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? propagation delay time clock to q, q t plh , t phl = (1.7 ns/pf) c l + 90 ns t plh , t phl = (0.66 ns/pf) c l + 42 ns t plh , t phl = (0.5 ns/pf) c l + 25 ns ????? ? ??? ? ? ??? ? ????? t plh t phl ???? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? ? ? ? ???? ? ?? ? ? ?? ? ???? 175 75 50 ???? ? ?? ? ? ?? ? ???? 350 150 100 ??? ? ? ? ? ? ? ??? ns ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? set to q, q t plh , t phl = (1.7 ns/pf) c l + 90 ns t plh , t phl = (0.66 ns/pf) c l + 42 ns t plh , t phl = (0.5 ns/pf) c l + 25 ns ????? ? ??? ? ? ??? ? ????? ???? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? ? ? ? ???? ? ?? ? ? ?? ? ???? 175 75 50 ???? ? ?? ? ? ?? ? ???? 350 150 100 ??? ? ? ? ? ? ? ??? ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? reset to q, q t plh , t phl = (1.7 ns/pf) c l + 265 ns t plh , t phl = (0.66 ns/pf) c l + 67 ns t plh , t phl = (0.5 ns/pf) c l + 50 ns ????? ? ??? ? ? ??? ? ????? ???? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? ? ? ? ???? ? ?? ? ? ?? ? ???? 225 100 75 ???? ? ?? ? ? ?? ? ???? 450 200 150 ??? ? ? ? ? ? ? ??? ??????????????? ? ????????????? ? ??????????????? setup times (7) ????? ? ??? ? ????? t su ???? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ???? 40 20 15 ???? ? ?? ? ???? 20 10 7.5 ???? ? ?? ? ???? ? ? ? ??? ? ? ? ??? ns ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? hold times (7) ????? ? ??? ? ? ??? ? ????? t h ???? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? 40 20 15 ???? ? ?? ? ? ?? ? ???? 20 10 7.5 ???? ? ?? ? ? ?? ? ???? ? ? ? ??? ? ? ? ? ? ? ??? ns ??????????????? ? ????????????? ? ??????????????? clock pulse width ????? ? ??? ? ????? t wl , t wh ???? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ???? 250 100 70 ???? ? ?? ? ???? 125 50 35 ???? ? ?? ? ???? ? ? ? ??? ? ? ? ??? ns ??????????????? ? ????????????? ? ??????????????? clock pulse frequency ????? ? ??? ? ????? f cl ???? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ???? ? ? ? ???? ? ?? ? ???? 4.0 10 14 ???? ? ?? ? ???? 2.0 5.0 7.0 ??? ? ? ? ??? mhz ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? clock pulse rise and fall time ????? ? ??? ? ? ??? ? ????? t tlh t thl ???? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? ? ? ? ???? ? ?? ? ? ?? ? ???? ? ? ? ???? ? ?? ? ? ?? ? ???? 15 5.0 4.0 ??? ? ? ? ? ? ? ??? s ??????????????? ? ????????????? ? ??????????????? set and reset pulse width ????? ? ??? ? ????? t wl , t wh ???? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ???? 250 100 70 ???? ? ?? ? ???? 125 50 35 ???? ? ?? ? ???? ? ? ? ??? ? ? ? ??? ns ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? removal times set ????? ? ??? ? ? ??? ? ????? t rem ???? ? ?? ? ? ?? ? ???? 5 10 15 ???? ? ?? ? ? ?? ? ???? 80 45 35 ???? ? ?? ? ? ?? ? ???? 0 5 5 ???? ? ?? ? ? ?? ? ???? ? ? ? ??? ? ? ? ? ? ? ??? ns ??????????????? ? ????????????? ? ??????????????? reset ????? ? ??? ? ????? ???? ? ?? ? ???? 5 10 15 ???? ? ?? ? ???? 50 30 25 ???? ? ?? ? ???? 35 10 5 ???? ? ?? ? ???? ? ? ? ??? ? ? ? ??? 5. the formulas given are for the typical characteristics only at 25 c. 6. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. 7. data must be valid for 250 ns with a 5 v supply, 100 ns with 10 v, and 70 ns with 15 v. logic diagram (1/2 of device shown) r c d s c c cc c c c c c c q q
mc14013b http://onsemi.com 5 figure 1. dynamic signal waveforms (data, clock, and output) figure 2. dynamic signal waveforms (set, reset, clock, and output) 20 ns 20 ns d c q 90% 50% 10% t su (h) t su (l) t h t wh t wl 90% 50% 10% v dd v ss v dd v ss v oh v ol t tlh t thl t phl t plh 90% 50% 10% inputs r and s low. 1 f cl 20 ns 20 ns set or reset clock q or q 90% 50% 10% v dd v ss v dd v ss v oh v ol 20 ns 20 ns t rem 90% 50% 10% 50% t plh t phl t w 20 ns t w typical applications n?stage shift register binary ripple up?counter (divide?by?2 n ) modified ring counter (divide?by?(n+1)) d clock n th 2 1 q d c q q d c q q d c q q clock n th 2 1 d c q q d c q q d c q q q t flip-flop n th 2 1 q d c q q d c q q d c q q clock
mc14013b http://onsemi.com 6 package dimensions pdip?14 p suffix case 646?06 issue n 17 14 8 b a dim min max min max millimeters inches a 0.715 0.770 18.16 18.80 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l m ??? 10 ??? 10 n 0.015 0.039 0.38 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. f hg d k c seating plane n ?t? 14 pl m 0.13 (0.005) l m j 0.290 0.310 7.37 7.87 soic?14 d suffix case 751a?03 issue g notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ?a? ?b? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ?t? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019
mc14013b http://onsemi.com 7 package dimensions tssop?14 dt suffix case 948g?01 issue o dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ?u? seating plane 0.10 (0.004) ?t? ??? ??? section n-n detail e j j1 k k1 detail e f m -w- 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ?v? 14x ref k n n
mc14013b http://onsemi.com 8 package dimensions soeiaj?14 f suffix case 965?01 issue o h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 1.42 --- 0.056 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1 dimensioning and tolerancing per ansi y14.5m, 1982. 2 controlling dimension: millimeter. 3 dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4 terminal numbers are shown for reference only. 5 the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). 0.13 (0.005) m 0.10 (0.004) d z e 1 14 8 7 e a b view p c l detail p m a b c d e e 0.50 m z on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 mc14013b/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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